1. Field of the Invention
The present invention relates to the design of erasable and programmable non-volatile memory devices; and more particularly to circuits for erasing memory cells in FLASH EPROM devices.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as the erasable-programmable read only memory (EPROM). Two popular EPROM designs are distinguished in the manner in which isolation of the memory cells is carried out. The first is referred to as the EEPROM. A second member of this class is known as the FLASH EPROM which uses a higher density format.
Both the FLASH EPROM and EEPROM technologies are based on a memory cell which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons which causes the turn-on threshold of the memory cell to increase. Thus, when programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
Both the FLASH EPROM and EEPROM memory cells suffer the problem of over-erasure. Over-erasure occurs if, during the erasing step, too many electrons are removed from the floating gate leaving a slight positive charge. This biases the memory cell slightly on, so that a small current may leak through the memory cell even when it is not addressed. A number of over-erased cells along a given bitline can cause an accumulation of leakage current sufficient to cause a false reading. The regular EEPROM design use either a two transistor cell structure which includes a pass gate that isolates the memory cell from the bitline or a split-gate structure which behaves like two transistors in series to isolate un-selected cells, so that unselected memory cells do not contribute leakage current to the bitline. The higher density FLASH EPROM cell does not use the isolation transistor or split-gate, so over-erasure causes a significant problem in the FLASH EPROM design.
When floating gate cells are over-erased, it makes it difficult to reprogram the cells successfully using hot electron programming, particularly with embedded algorithms in the integrated circuits that cannot handle special cases.
Further, commercial FLASH EPROM designs include circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,188, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth.
Traditionally, erase verification begins at address 0000 (hex) and continues through the array to the last address, or until data other than FF (hex) is encountered. If a byte fails to verify, the entire device is re-erased. This re-erase operation may result in over-erasure of memory cells that had passed the erase verify voltage margin during the initial erase operation.
Also, the re-erase operation is time consuming, requiring re-verification of the entire array after each re-erase operation.
Accordingly, an erase verify and re-erase system for FLASH EPROM devices is needed which protects against over-erase due to repeated erasures, and which speeds up the verify sequence.